High level synthesis of pipelined instruction set processors and back-end compilers

Abstract

The authors propose a synthesis methodology for high-performance pipelined instruction set processors. Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of the Advanced Design Automation System (ADAS) which controls the hardware-software interactions at the micro-architecture level. The key function of Piper is to perform pipeline scheduling with any fixed instruction-latency, and generate a reorder table for a back-end compiler to resolve potential pipeline hazards existing in the design. Models for performance and cost of both hardware and software are developed to characterize the design space. A synthesis example of a simple instruction set processor illustrates Piper's synthesis capabilities and how the performance and cost of hardware and software are estimated. >