ACM SIGARCH Computer Architecture News · 2004 · 14 citations · 9 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsLow-power DesignEnergy-efficient Embedded SystemsMemory Subsystem DesignMicroarchitecture DesignPower ManagementProcessor Core DesignProcessor MicroarchitectureEmbedded Processor DesignLow-power Embedded DesignLow-power MicroarchitectureLow-power Processor DesignOn-chip Memory DesignPipeline ArchitecturePower-efficient DesignRecovery Time
A SuperH™ embedded processor core SH-X implemented in a 130-nm CMOS process running at 400 MHz achieved 720 MIPS and 2.8 GFLOPS at a power of 250 mW under worst-case conditions. It has a dual-issue seven-stage pipeline architecture, but reaches the 1.8 MIPS/MHz of the previous five-stage processor. The on-chip memory configuration is tuned for digital consumer appliances. A new resume-standby mode enables a standby current of less than 100, μA and a 3-ms recovery time. The processor meets the requirements of a wide range of applications, and is suitable for digital appliances aimed at the consumer market, such as cellular phones, digital still/video cameras, and car navigation systems.
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Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda et al. · IEEE Journal of Solid-State Circuits · 2005 · 99 citations
Engineering, Computer Engineering, Electrical Engineering +17
A resume-standby application processor for 3G cellular phones
T. Kamei, Masatoshi Ishikawa, T. Hiraoka et al. · 2004 · 42 citations
SH4 RISC multimedia microprocessor
F. Arakawa, Osamu Nishii, K. Uchiyama et al. · IEEE Micro · 1998 · 32 citations