A unified switching theory with applications to VLSI design

John P. Hayes

Proceedings of the IEEE · 1982 · 89 citations · 10 references

Concepts

TL;DR

Classical switching theory is shown to have deficiencies when applied to the analysis and design of MOS VLSI circuits. The paper introduces CSA theory, a new logic design methodology that addresses these deficiencies in MOS VLSI circuit analysis and design. CSA theory models MOS VLSI circuits using connectors, switches, and attenuators, supports four (or more) logic values—including 0, 1, U, and Z—leverages logical strength to capture current drive, and incorporates a well element for sequential behavior. Using CSA network models, the authors demonstrate that most MOS logic circuits can be uniformly and rigorously modeled with four or seven logic values, and they apply the theory to inverter synthesis and fault simulation.

Abstract

Classical switching theory is shown to have deficiencies when applied to the analysis and design of MOS VLSI circuits. A new logic design methodology called CSA theory is described here which overcomes many of these deficiencies. It is based on three primitive component types: connectors that perform wired-logic operations, switches representing controlled connectors, and attenuators representing resistive load devices. Four basic types of logic values are recognized: Boolean 0 and 1 values, unknown or indeterminate U values, and the high-impedance state Z. The number of logic values can be increased systematically to improve modeling accuracy using a concept of logical strength, which corresponds to current drive capability in analog circuits. It is shown that both the behavior and layout of most types of MOS logic circuits, including contact, gate, and nonclassical mixed circuits, can be treated in a uniform and rigorous manner using CSA network models with either four or seven logic values. The use of a digital charge-storage element called a well to represent sequential behavior is examined. CSA theory is applied to two VLSI design issues, inverter synthesis and fault simulation.

References

10