1c:I[419806,["/_next/static/chunks/bb923814e1f4d2e9.js","/_next/static/chunks/dd3ee9f5b7716ca6.js","/_next/static/chunks/4204a0ae82542ca8.js","/_next/static/chunks/30036bedc5269936.js","/_next/static/chunks/6e1aa89a642f40be.js","/_next/static/chunks/cd5e572bc3e4eb92.js","/_next/static/chunks/8ffd0b71567920d8.js","/_next/static/chunks/67ea6dfd21f16c5f.js","/_next/static/chunks/24eb4379f68013fd.js","/_next/static/chunks/b8cd775ffdf935bd.js","/_next/static/chunks/983103cd9eb7b428.js","/_next/static/chunks/d4ac9dcf27f6ff52.js","/_next/static/chunks/294b9525248c8e5f.js"],"default"] 1d:T42a,HEED and Auger electron spectroscopy have been used to evaluate silicon cleaning by sequential immersions in basic and acidic peroxide solutions. It was determined that an oxide film 13–15Aå thick was left after the cleaning. This film contained boron at a surface concentration estimated at 1013–1014 B/cm2. The carbide contamination that results upon heating to 800°C in ultra‐high vacuum was dramatically reduced when compared to wafers cleaned with other techniques. Wafers cleaned with the same process except for a final HF etch had no detectable boron in the surface oxide, formed relatively large amounts of surface silicon carbide at 800°C, and suffered extensive surface roughening with 1100°C heating in vacuum. The protective mechanism of the peroxide cleaning is thought to be due to formation of a thin nearly carbon free oxide layer that volatilizes when the wafers are heated in ultrahigh vacuum. It is recommended that experiments requiring a solvent type cleaning and the heating of Si in ultrahigh vacuum should use this cleaning method.1e:T523,MBE growth and infrared device fabrication with epitaxial IV-VI layers on Si substrates are reviewed. Epitaxy on Si substrates is achieved using a stacked BaF₂/CaF₂ or CaF₂ buffer layer. With buffers containing no BaF₂, standard photolithographic delineation with wet-etching techniques can be used. Photovoltaic IV-VI sensors with cutoff wavelengths ranging from 3 to 14 μm are fabricated in PbS, PbSe_1-xS_x, PbEu_1-xSe_x, PbTe, or Pb_1-xSn_xSe layers on Si (111) substrates. They offer the possibility for low-cost infrared focal plane arrays with sensitivities similar to Hg_1-xCd_xTe, but with much less demanding material processing steps. A 13-mm-long linear array with 10.5-μm cutoff wavelength has inhomogeneities in cutoff below 0.1 μm. Some arrays were grown on prefabricated active Si substrates containing the whole readout circuits. First thermal images using these chips are demonstrated. The induced mechanical strain resulting from the different thermal expansion of IV-VIs and Si relaxes down to cryogenic temperatures even after many temperature cycles because of dislocation glide in the main {100} glide planes.1f:T5a0,

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