Controlled misfit dislocation technology in strained silicon MOSFETs

Abstract

In this paper, we report new process integration flows to fabricate strained-Si nMOSFETs having thicker strained-Si grown on a relaxed Si0.8Ge0.2 virtual substrate. For the same device parameters and process condition, a device with this advanced integration flow (sample B) starting epitaxial strained-Si layers after shallow trench isolation and well implantation is shown having a 70% enhancement in effective electron mobility compared to the Si control device. Devices with conventional process sequences (sample A) exhibit a larger leakage current and up to 50% device failure. The leakage mechanism in sample A due to misfit dislocation-induced leakage paths is clearly demonstrated from the photon emission microscopy (PEM) measurement. Improved characteristics in sample B indicate that devices with new process sequences exhibit controlled misfit dislocations in strained-Si layers and show a greater flexibility for developing high-performance strained-Si CMOS.