IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009 · 21 citations · 19 references
ComputingComputer EngineeringComputer ScienceAlgorithmsCryptographyMicroelectronicsCryptographic AlgorithmsCryptographic ArchitectureHardware AccelerationEncryptionFinite Field ArithmeticLow-power MultipliersMultiplier DesignMultipliersThroughput
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <?Pub Dtl=""?>This paper presents a highly efficient multimode multiplier supporting prime field, namely, polynomial field, and matrix–vector multiplications based on an asymmetric word-based Montgomery multiplication (MM) algorithm. The proposed multimode 128 <formula formulatype="inline"> <tex Notation="TeX">$\times$</tex></formula> 32 b multiplier provides throughput rates of 441 and 511 Mb/s for 256-b operands over <formula formulatype="inline"> <tex Notation="TeX">$GF(P)$</tex></formula> and <formula formulatype="inline"> <tex Notation="TeX">$GF(2^n)$</tex></formula> at a clock rate of 100 MHz, respectively. With 21 930 additional gates for Advanced Encryption Standard (AES), the multiplier is extended to provide 1.28-, 1.06-, and 0.91-Gb/s throughput rates for 128-, 192-, and 256-b keys, respectively. The comparison result shows that the proposed integration architecture outperforms others in terms of performance and efficiency for both AES and MM that is essential in most public-key cryptosystems. </para>
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Handbook of applied cryptography
Choice Reviews Online · 1997 · 10.5K citations · Full text
Modular multiplication without trial division
Peter L. Montgomery · Mathematics of Computation · 1985 · 2.4K citations
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Peter L. Montgomery · Mathematics of Computation · 1985 · 1.1K citations · Full text