Considerations for Single Event Immune VLSI Logic

Abstract

The applicability of resistive decoupling and other hardening techniques to circuits and chip level systems at very large scales of integration and at very high signal speeds is considered. Circuits may sustain soft errors due to ion interactions with non-RAM logic. The modes of ion-induced error production in non-memory circuitry are identified and methods of upset reduction or prevention determined to produce single event immune circuit designs. The applicability of hardening methods to logic of smaller size and/or higher speed is identified. Established computer simulation methods are used to predict limitations for single event immune integrated circuits. The single event problem is defined and characterized at a chip level, and criteria are suggested for optimizing designs for use in ion environments. (LEW)