Statistical delay computation considering spatial correlations

TLDR

Process variation is a major concern for static timing analysis. The study introduces a new path‑based statistical timing analysis method. The authors model inter‑ and intra‑die device‑length variations, compute path‑delay probability distributions by enumerating inter‑die lengths and analytically treating intra‑die lengths, incorporate a simple spatial‑correlation model, and validate the approach on industrial microprocessor paths using data from eight test chips. The method accurately predicts path delays, matching Monte‑Carlo simulations and outperforming traditional analyses that ignore inter‑ and intra‑die variation distinctions.

Abstract

Process variation has become a significant concern for static timing analysis. In this paper, we present a new method for path-based statistical timing analysis. We first propose a method for modeling inter- and intra-die device length variations. Based on this model, we then present an efficient method for computing the total path delay probability distribution using a combination of device length enumeration for inter-die variation and an analytical approach for intra-die variation. We also propose a simple and effective model of spatial correlation of intra-die device length variation. The analysis is then extended to include spatial correlation. We test the proposed methods on paths from an industrial high-performance microprocessor and present comparisons with traditional path analysis which does not distinguish between inter- and intra-die variations. The characteristics of the device length distributions were obtained from measured data of 8 test chips with a total of 17688 device length measurements. Spatial correlation data was also obtained from these measurements. We demonstrate the accuracy of the proposed approach by comparing our results with Monte-Carlo simulation.