A 2.45GHz CMOS power amplifier with high linearity

Abstract

A 2.45 GHz 0.18 ¿m RF CMOS Class-AB power amplifier (PA) with high linearity and output power for WLAN is presented in this paper. The proposed power amplifier is implemented with a two-stage architecture which is followed by an off-chip output matching network. To improve the linearity, an integrated diode linearization circuit provides a compensation mechanism for the input capacitance variation of the active devices, improving the linearity from the gain compressing. Moreover, a simple LC second harmonic tank and optimum gate biasing point is applied for the cancellation of the nonlinear harmonic generated by g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> . In order to demonstrate the feasibility of the technique, two types of PAs have been designed. The improved PA at 2.4V supply voltage, has a 22.5 dB of power gain, 5 dBm increase of P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> , 15% and 5 dB improvement of PAE at P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> and IMD3, respectively, as compared with the traditional PA..