A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard

Abstract

A fully integrated CMOS direct-conversion 5-GHz transceiver with automatic frequency control is implemented in a 0.18-μm digital CMOS process and housed in an LPCC-48 package. This chip, along with a companion baseband chip, provides a complete 802.11a solution The transceiver consumes 150 mW in receive mode and 380 mW in transmit mode while transmitting +15-dBm output power. The receiver achieves a sensitivity of better than -93.7dBm and -73.9dBm for 6 Mb/s and 54 Mb/s, respectively (even using hard-decision decoding). The transceiver achieves a 4-dB receive noise figure and a +23-dBm transmitter saturated output power. The transmitter also achieves a transmit error vector magnitude of -33 dB. The IC occupies a total die area of 11.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and is packaged in a 48-pin LPCC package. The chip passes better than ±2.5-kV ESD performance. Various integrated self-contained or system-level calibration capabilities allow for high performance and high yield.