Low-loss, wideband SPDT switches and switched-line phase shifter in 180-nm RF CMOS on SOI technology

Abstract

Low-loss, wideband (DC to 40 GHz) single-pole double-throw (SPDT) RF switches implemented in a 180 nm SOI CMOS technology are presented. A π-matching network is implemented to improve the insertion loss (IL) at high frequencies. The differences between the conventional inductive peaking and the matching network utilized here are discussed. Under nominal conditions, the IL of the 1.5 V switch is less than 0.5 dB from DC to 20 GHz; and less than 2.0 dB at 40 GHz. The input matching of the switch is better than 10 dB, the isolation (ISO) is greater than 15 dB, and the P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of the 1.5 V switch is 11 dBm. A higher voltage (2.5 V) switch implemented with high-breakdown devices increases the P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> to 15 dBm at the cost of a small increase in IL. A switched-line one-bit 180° phase shifter (PS) is demonstrated using the 1.5 V low-loss switch. The PS exhibits an IL better than 3 dB at 18 GHz. The advantages of implementing a low-loss switch in a 180 nm technology are discussed.