Logic Performance of 40 nm InAs HEMTs

Abstract

We have experimentally evaluated the logic performance of 40 nm InAs HEMTs. For a barrier thickness of 4 nm, we find that 40 nm InAs HEMTs exhibit excellent logic figures of merit and scalability at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V, such as DIBL = 80 mV/V, S = 70 mV/dec, and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> = 475 GHz. These remarkable results arise from the combination of the outstanding transport properties of InAs channel, and the use of a thin insulator and a thin channel. In addition, these devices exhibit I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratios in excess of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> , revealing that band-to-band tunneling is not a significant concern in our device design. Our InAs HEMTs exhibit an injection velocity at the virtual source point that is a factor of 1.6X higher than state-of-the-art Si n-MOSFETs, in spite of the significantly lower supply voltage.