Low-power high-speed InP MISFET direct-coupled FET logic

Abstract

High-dynamic-range n-channel InP MISFET direct-coupled FET logic ring oscillator and inverter integrated circuits with minimum observed propagation delay per stage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t_{pd} = 62</tex> ps with associated power delay product of 41 fJ and minimum observed power delay product <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Pt_{pd} = 22</tex> fJ with associated delay of 84 ps have been fabricated on Fe-doped semi-insulating substrate material using ion implantation for contact and load channel regions and pyrolytic SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> as the gate insulator. Accumulation-type enhancement-mode MISFET structures with source-drain separations of 1.5 µm and gate metallization lengths of 3.0 µm were employed as driver devices while both MESFET's and 1.5-µm-length ungated "velocity saturation" structures were used as loads. With <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_{DD} = 4.5</tex> V representative inverter structures exhibited logic swings of 3.58 V, noise margins of 1.00 and 0.92 V, and dc gain in the linear region of 2.2.