Low-Power CMOS Digital Design

Anantha P. Chandrakasan, S. Sheng, R.W. Brodersen

Low-power CMOS digital design

Anantha P. Chandrakasan, Samuel Sheng, R.W. Brodersen

IEEE Journal of Solid-State Circuits

EngineeringEnergy EfficiencyPower Optimization (Eda)Computer ArchitecturePower Optimization +17

Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits

Harry Veendrick

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignCircuit System +12

Limits of instruction-level parallelism

David W. Wall

EngineeringComputer ArchitectureSoftware EngineeringAlias AnalysisSoftware Analysis +16

Physics of Semiconductor Devices

Materials Today

SemiconductorsSemiconductor DevicesElectrical EngineeringSemiconductor TechnologyEngineering +4

Comparing algorithm for dynamic speed-setting of a low-power CPU

Kinshuk Govil, Edwin Sing-Long Chan, Hal Wasserman

EngineeringHardware AlgorithmComputer ArchitectureArticle Comparing AlgorithmComputing Systems +14

Low-power digital design

Mark Horowitz, T. Indermaur, R. Gonzalez

EngineeringEnergy EfficiencyPower Optimization (Eda)Computer ArchitectureCmos Circuits +16

Instruction level power analysis and optimization of software

Vivek Tiwari, Sharad Malik, Andrew Wolfe, +1

The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology

EngineeringProgram AnalysisPower Optimization (Eda)Software TestingComputer Engineering +8

The multiflow trace scheduling compiler

P. Geoffrey Lowney, Stefan M. Freudenberger, Thomas J. Karzes, +4

The Journal of Supercomputing

EngineeringProgram AnalysisCompiler TechnologyCompiler SupportComputer Engineering +9

Available instruction-level parallelism for superscalar and superpipelined machines

Norman P. Jouppi, D. W. Wall

ACM SIGARCH Computer Architecture News

Functional UnitEngineeringSupercomputer ArchitectureProgram AnalysisParallelizing Compiler +11