Passivation of InP-Based Heterostructure Bipolar Transistors in Relation to Surface Fermi Level

Abstract

The effect of surface Fermi level position on dc-characteristics of InP-based heterostructure bipolar transistors (HBT) is reported. The Fermi level of an InP surface covered with silicon oxide was located at an energy position close to the conduction band minimum of InP. This implies that an electron accumulation layer forms at the interface, which acts as a surface leakage path. The HBT passivated with silicon oxide films showed large excess base current and poor current gain. In contrast, the Fermi level position at the silicon nitride/InP interface was found to be near the midgap, and no electron accumulation layer was formed at the interface. The HBT passivated with silicon nitride film showed excellent dc characteristics with very small, excess base current.