A 24GS/s 6b ADC in 90nm CMOS

Abstract

This paper presents a 24 GS/s 6 b ADC in 90 nm CMOS with the highest ENOB up to 12 GHz input frequency and lowest power consumption of 1.2 W compared to ADCs with similar performance. It uses an interleaved architecture of SAR type self-calibrating converters operating from 1 V supply combined with an array of 2.5 V T/Hs with delay, gain and offset-calibration capability.