Double-Emitter Reduced-Surface-Field Horizontal Current Bipolar Transistor With 36 V Breakdown Integrated in BiCMOS at Zero Cost

Abstract

A novel double-emitter horizontal current bipolar transistor (HCBT) with reduced-surface-field (RESURF) region is presented. The structure is integrated with standard 0.18-μm CMOS, together with high-speed HCBT with BVCEO = 3.6 V and double-emitter HCBT with BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> = 12 V. The second RESURF drift region is formed using a standard CMOS p-well implant for the formation of local substrate below the extrinsic collector. Collector-emitter breakdown is completely avoided by the E-field shielding. Breakdown occurs between the collector and the substrate and equals 36 V. The transistor is fabricated in HCBT BiCMOS process flow without the additional process steps and the use of additional lithography masks.