10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS

Abstract

High-speed serial links integrated in advanced CMOS are ubiquitous in modern microprocessor systems. These commodity links have fixed performance specs and therefore realize the benefit of technology scaling in area and power reduction at high data rates. To realize significant scaling benefits, these designs must overcome the challenges associated with implementing analog functions in scaled logic-optimized processes while maintaining link robustness over a wide range of channel characteristics and third party components.This work describes a 2.5-to-10 Gb/s serial link implemented in 14nm tri-gate CMOS using logic-pitch transistors exclusively. The half-rate embedded-clock transceiver architecture consists of a 3-tap current-mode (CM) TX, an RX with a CTLE, a 4-tap integrating DFE, and a phase-interpolator-based CDR. It is 60% smaller and consumes 11% less energy per bit than reported links at comparable data rates and channel losses. It also introduces a baud-rate CDR algorithm that uses the real-time extracted channel response at the DFE to optimize the sampling point, relaxes the headroom/swing tradeoff at the TX driver by using dynamic signal boosting, eliminates the process cost for a precision resistor by using tunable serpentine resistors, and includes a low-power and low-area RX squelch circuit with a digital peak detector.