Wafer bin map recognition using a neural network approach

Abstract

Although the fabrication of modern integrated circuits uses highly automatic and precisely controlled operations, equipment malfunctions or process drifts are still inevitable owing to the high complexity involved in the hundreds of processing steps. To detect the existence of these problems at the earliest stage, some important analytical tools must be applied. Among them is wafer bin map analysis. When the bin map exhibits specific patterns, it is usually a clue that equipment problems or process variations have occurred. The aim was to develop an intelligent system that could automatically recognize wafer bin map patterns and aid in the diagnosis of failure causes. A neural network architecture named Adaptive Resonance Theory Network 1 was adopted for the purpose. Actual data collected from a semiconductor manufacturing company in Taiwan were used for system verification. Experimental results show that with an adequate parameter, the neural network can successfully recognize and distinguish random and systematic wafer bin map patterns.