Automated generation of DSP program development tools using a machine description formalism

Abstract

The authors introduce a retargetable microcode generator for application specific digital signal processors (ASDSPs). The primary goal is to provide quickly system architects with the set of tools necessary for program development (assemblers, instruction set simulators, debuggers, and compilers), particularly when the processor architecture is refined simultaneously with the algorithm. After a modification of the architecture, only the machine description written in the language nML must be altered; the tools are then produced automatically. The machine description need not explicitly list every possible instruction in full length. Instead, a derivation tree is described. Through the extensive use of inheritance and sharing of properties, this description can be very compact. Based on the latter, the recognition of critical data paths and the analysis of machine inherent parallelism is solely performed by the tool generator.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>