A method of redundant clocking detection and power reduction at RT level design

Abstract

Article Free Access Share on A method of redundant clocking detection and power reduction at RT level design Authors: Mitsuhisa Ohnishi Precision Technology Development Center, Sharp Corporation, 2613-1, Ichinomoto, Tenri, Nara 632, Japan Precision Technology Development Center, Sharp Corporation, 2613-1, Ichinomoto, Tenri, Nara 632, JapanView Profile , Akihisa Yamada Precision Technology Development Center, Sharp Corporation, 2613-1, Ichinomoto, Tenri, Nara 632, Japan Precision Technology Development Center, Sharp Corporation, 2613-1, Ichinomoto, Tenri, Nara 632, JapanView Profile , Hiroaki Noda Precision Technology Development Center, Sharp Corporation, 2613-1, Ichinomoto, Tenri, Nara 632, Japan Precision Technology Development Center, Sharp Corporation, 2613-1, Ichinomoto, Tenri, Nara 632, JapanView Profile , Takashi Kambe Precision Technology Development Center, Sharp Corporation, 2613-1, Ichinomoto, Tenri, Nara 632, Japan Precision Technology Development Center, Sharp Corporation, 2613-1, Ichinomoto, Tenri, Nara 632, JapanView Profile Authors Info & Claims ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and designAugust 1997 Pages 131–136https://doi.org/10.1145/263272.263307Published:01 August 1997Publication History 23citation177DownloadsMetricsTotal Citations23Total Downloads177Last 12 Months6Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF