2014 · 22 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsDigital Signal ProcessingLow-power Digital Circuit DesignPower ManagementPower OptimizationPower-aware DesignAnalog-to-digital ConversionAnalog-to-digital Converter DesignDifference Equation ModelsDigital-to-analog Converter DesignFirst-order Difference EquationsLow-power Cmos DesignPower Conversion EfficiencyPower Efficiency
In this paper we present a scaling friendly supplement to ADC designs which can produce increases in conversion speed and power efficiency by attempting to predict the value of the next sample. To accomplish this we use a first order difference equation to predict the values of several of the bits in the next sample. In doing so, we can save power by reducing the number of comparisons and by reducing the capacitor array switching power.
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11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS
Hung-Yen Tai, Yao-Sheng Hu, Hung‐Wei Chen et al. · 2014 · 222 citations
Engineering, Computer Engineering, Electrical Engineering +17