Correction to “A 15-Bit 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration”

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

E. Siragusa, Ian Galton · IEEE Journal of Solid-State Circuits · 2004 · 209 citations

Engineering, Electrical Engineering, Analog Electronics +16

Digital cancellation of D/A converter noise in pipelined A/D converters

Ian Galton · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2000 · 140 citations

Engineering, Computer Engineering, Electrical Engineering +17

Gain error correction technique for pipelined analogue-to-digitalconverters

E. Siragusa, Ian Galton · Electronics Letters · 2000 · 89 citations

Engineering, Electrical Engineering, Analog Electronics +11

A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration

Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu · IEEE Journal of Solid-State Circuits · 2005 · 82 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 96 dB SFDR 50 MS/s digitally enhanced CMOS pipeline A/D converter

K. Nair, R. Harjani · 2004 · 43 citations

Engineering, Computer Engineering, Electrical Engineering +17