Improvement of Read Margin and Its Distribution by $V_{\rm TH}$ Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection

Abstract

A <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> mismatch self-repair scheme in 6T-SRAM with asymmetric pass gate transistor by post-process local electron injection is proposed. Local electron injection is automatically and simultaneously achieved to either pass gate transistor that most increases the read margin for each cell without investigating its characteristics. The proposed asymmetric <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> shift is twice as large as the conventional scheme without process and cell area penalty. Measurement results show 20% increase in SNM without write degradation by the asymmetric PG transistor. The proposed scheme also enhances the minimum read margin by 70% while reducing read margin distribution by 20%, thanks to the self-repair function.