Leakage current models of thin film silicon-on-insulator devices

Abstract

Thin film silicon-on-insulator (SOI) devices have an advantage of excellent isolation due to the buried oxide layer leading to reduced capacitance coupling and no latchup in complementary metal-oxide-silicon circuits compared with bulk silicon devices. Reduced junction area should lead to lower leakage for a given device. However, because of the buried oxide, stress is built up in the Si island during isolation processes, especially near the island edges, inducing new kinds of leakage currents, which are not observed in bulk silicon devices. This letter proposes five leakage current models of the partially depleted SOI devices, identifies their origins, and suggests methods to prevent each type.