ACM SIGARCH Computer Architecture News · 1997 · 10 citations · 0 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureData StructuresExperimental PerformanceBenchmarkingCachingCaching StrategiesInstruction Set ArchitectureMemory Hierarchy DesignMemory Subsystem DesignCache AnalysisCache Hit Rate OptimizationCache Miss AnalysisCache OptimizationCache Replacement PoliciesCache SimulationCache Trace AnalysisPage Replacement Algorithms
In this paper, we propose a new strategy (KORA-2) for the replacement of lines in cache memories. The algorithm is efficient and easily implementable. It is basically an extension of our previous work presented in [1]-[5]. Key to our algorithm is to identify and discard inactive lines relatively quickly as opposed to the conventional replacement algorithms. Trace-driven simulations were performed for 42 different cache configurations using benchmark programs from SPEC92 (Standard performance Evaluation Corporation) benchmark suites. Simulation results illustrate that our algorithm can provide a peak value of approximately 8.71% improvement in the miss ratio over the best performing conventional algorithm (LRU) for the selected benchmark trace files generated from SPEC programs. This translates to a savings of hundreds of thousands of misses for typical programs referencing well over 100 million addresses.