Acoustic coprocessor for hmm based embedded speech recognition systems

Abstract

This paper describes a hardware accelerator for calculating observation probabilities in Hidden Markov Model based embedded speech recognition systems. The architecture integrates an 8-way data-path with a high bandwidth NOR Flash array and calculates senone scores for all senones in the acoustic library. This improves system response time by a factor of 2 (compared to software solutions running on just the embedded CPU), while consuming only 210mW power. The reduced recognition latency enables use of larger acoustic models thereby reducing the recognition word error rate by 15.4%. The hardware supports scoring of some or all senones in the acoustic library and speaker adaptation using feature vector transforms <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> .