2015 · 83 citations · 6 references
Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureMulti-channel Memory Architecture3D Memory3D-stacking TechnologyAdvanced Packaging (Semiconductors)V-nand Flash MemoryMemory DevicesElectronic PackagingParallel ComputingMost Memory-chip ManufacturersDie Size3D Ic ArchitectureElectrical EngineeringI/o RateFlash MemoryComputer EngineeringMicroelectronicsMemory Architecture3D PrintingSemiconductor Memory
Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].
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19.1 A 128Gb MLC NAND-Flash device using 16nm planar cell
Mark Helm, Jaekwan Park, Ali Ghalam et al. · 2014 · 67 citations
Non-volatile Memory, Engineering, Emerging Memory Technology +23
A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology
Daeyeal Lee, Ik‐Joon Chang, Sang-Yong Yoon et al. · 2012 · 48 citations
Hardware Security, Non-volatile Memory, Electrical Engineering +11