Parallel reduced area multipliers

A Suggestion for a Fast Multiplier

Christopher S. Wallace · IEEE Transactions on Electronic Computers · 1964 · 1.8K citations

Engineering, Computer Architecture, Supercomputer Architecture +19

A SIGNED BINARY MULTIPLICATION TECHNIQUE

A. D. Booth · The Quarterly Journal of Mechanics and Applied Mathematics · 1951 · 1.3K citations

Hardware Security, Cryptographic Primitive, Engineering +15

A Two's Complement Parallel Array Multiplication Algorithm

C.R. Baugh, B.A. Wooley · IEEE Transactions on Computers · 1973 · 641 citations

Hardware Security, Array Computing, Engineering +12

SPIM: a pipelined 64*64-bit iterative multiplier

Mark R Santoro, Mark Horowitz · IEEE Journal of Solid-State Circuits · 1989 · 114 citations

Engineering, Vlsi Design, Pipelined Array +17

Fast Multipliers

Ali Habibi, P. A. Wintz · IEEE Transactions on Computers · 1970 · 105 citations

Hardware Security, Electrical Engineering, Fast Multiplier +14