A novel FPGA-based architecture for Sobel edge detection operator

Abstract

Abstract A novel FPGA-based architecture for Sobel edge detection algorithm has been proposed. The Sobel algorithm is chosen due to its property of providing a differencing as well as noise smoothing operation in the single kernel. Thus, noise sensitivity of first gradient based operations can be avoided by the use of this algorithm. The implementation of edge detection algorithms on a field programmable gate array (FPGA) is motivated by the fact that large memory FPGAs are now available, providing a platform for processing real time algorithms on application-specific hardware with substantially higher performance than programmable digital signal processors (DSPs). This architecture can be used as a building block of a pattern recognition system, autonomous robot navigation, and also as a system for creating an image dazzling effect in multimedia graphics. This architecture is implicitly pipelined to provide a system capable of operating at a clock speed of 99.499 MHz which is a significant improvement over programmable DSPs implementation. Keywords: Edge detection algorithmsFirst gradient based operatorsHardware implementationSobel operatorsVLSI