Test results of the Data Handling Processor for the DEPFET Pixel Vertex Detector

Abstract

In the new Belle II detector, which is currently under construction at the SuperKEKB accelerator, a two layer pixel detector will be introduced to improve the vertex reconstruction in a ultra high luminosity environment. The pixel detector will be produced using the DEPFET technology. A new ASIC (Data Handling Processor or DHP) designed to steer the readout process, pre-process and compress the raw data has been developed. The DHP will be directly bump bonded to the balcony of the all-silicon DEPFET module. The current chip prototype has been produced in CMOS 90 nm. Its test results, including the data processing quality, the signal integrity of the gigabit transmission lines will be presented here. For the final chip, which will be produced using CMOS 65 nm, single event upset (SEU) cross sections were measured. An additional chip, containing memory blocks to be tested, was submitted and produced using this technology.