Pipelined Hardware Structure for Sequency-Ordered Complex Hadamard Transform

Abstract

This letter presents a fast algorithm for the sequency-ordered complex Hadamard transform (SCHT) based on the decomposition method of decimation-in-sequency. To support high-speed real-time applications, a pipelined hardware structure is also proposed to deal with sequentially presented input/output data streams. This structure achieves a full hardware utilization and requires only complex adder/subtracters and complex data stores for an N-point SCHT.