Efficient encoding of QC‐LDPC codes based on rotate‐left‐accumulator circuits

Abstract

For efficient hardware implementation of QC‐LDPC encoders, four types of rotate‐left‐accumulator (RLA) circuits are proposed. Although the performance of a type I RLA circuit is exactly identical to the most widely used shift‐register‐adder‐accumulator (SRAA) circuit, its reasonable structure can derive the other three counterparts. Both type II and III RLA circuits are highly area efficient, and have the same speed as the SRAA circuit. Compared with these serial‐in circuits, the parallel‐in type IV RLA circuit is faster at the cost of more memory, and suitable for applications where generator matrices have fewer block rows or special parity‐check matrices are used to encode.