A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier

Abstract

This paper presents a 7-bit 1.5-GS/s time-interleaved (TI) SAR ADC. The scheme achieves better isolation between channels thanks to embedding a track-and-hold (T/H) amplifier and reference voltage buffer in each channel. The proposed dynamic T/H amplifier enables high-speed, low-power operation. The prototype is fabricated in a 65-nm CMOS technology. The total active area is 0.14mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the ADC consumes 36mW from a 1.2-V supply. The measured results show the peak spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are 52.4 dB and 39.6 dB, respectively, and an Figure of Merit (FoM) of 300 fJ/conv. is achieved.