Procedia Engineering · 2012 · 10 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDynamic Power ReductionLow-power Digital Circuit DesignPower OptimizationComparator DesignComparatorsEnergy-efficient Digital CircuitsLow-power Cmos DesignOffset VoltagePower ConsumptionPower Consumption ModelingTransmission Delay
In this paper, a high-speed low-power comparator, which is used in a 2 Gsps, 8 bit Flash ADC, is designed and simulated. Based on 0.18 um TSMC CMOS process model, the comparator circuit is simulated with a 1.8 V power supply in Cadence environment. The result shows that it can work at a 2GHZ clock frequency, and the dynamic power consumption is only 1.2mW, with 123.5ps transmission delay. In addition, the average offset voltage of this comparator is only 676.3uV, which can meet the requirements of an 8-bit Flash ADC.
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Low voltage comparator for high speed ADC
Hao Gao, Peter Baltus, Qiao Meng · 2010 · 10 citations
Engineering, Computer Engineering, Electrical Engineering +17