High-Level Synthesis for Accelerating the FPGA Implementation of Computationally Demanding Control Algorithms for Power Converters

Abstract

Recent advances in power electronic converters highly rely on the development of new control algorithms. These implementations often require complex control architectures featuring microprocessors, digital signal processors, and field-programmable gate arrays (FPGAs). Whereas software implementations are feasible for most power electronics practitioners, FPGA implementations with ad-hoc digital hardware are often a challenging design task. This paper deals with the design and development of control systems for power converters using high-level synthesis tools. In particular, the Xilinx Vivado HLS tool is evaluated for the design of a computationally demanding application, the real-time load estimation for resonant power converters using parametric identification methods. The proposed methodology allows the designer to use a high-level description language, e.g., C, to describe the identification algorithm functionality, and the tool automatically generates the hardware floating-point data-path and the control unit. Besides, it allows a fast design-space exploration through synthesis directives, and pipelining and parallelization are automatically performed to meet timing constraints. The evaluation performed in the study-case control architecture shows a significant design complexity reduction. As a consequence, high-level synthesis tools should be considered as a new paradigm in accelerating digital design for power conversion systems.