A 0.5-V 1.9-GHz Low-Power Phase-Locked Loop in 0.18-¿m CMOS

Abstract

Implemented in a standard 0.18-mum CMOS process, a 0.5-V 1.9-GHz low-power phase-locked loop (PLL) is presented. Due to the use of the forward-body-bias technique, the threshold voltage of the MOSFETs is effectively reduced, making it possible to operate the PLL at an ultra-low supply voltage. In addition, various techniques for low-power and low-voltage operations are also adopted in the design of the building blocks. With a dc power consumption of 4.5 mW, the fabricated PLL measures in-band and out-of-band phase noise of -83.4 dBc/Hz and -135.3 dBc/Hz at 100-kHz and 10-MHz frequency offset, respectively.