Publication | Closed Access
Field programmable gate array time counter with two-stage interpolation
28
Citations
7
References
2005
Year
Hardware SecurityTime Delay SystemPropagation TimeEngineeringClock RecoveryTiming AnalysisDelay LineComputer ArchitectureComputer EngineeringPrecise Time CounterTwo-stage InterpolationDigital Circuit DesignTimed SystemClock SynchronizationAsynchronous Circuits
This paper presents a precise time counter with two two-stage interpolators, integrated in a field-programmable gate array device. Interpolation is performed by a single tapped delay line with dual synchronizers in the first stage and a differential tapped delay line in the second stage. The delay-locked loop is used for indirect stabilization of the propagation time of delay elements. The counter has 200ps resolution over the measurement range of 0–167ms with the standard measurement uncertainty below 140ps. A detailed analysis of influence of the flip–flop metastability on the counter accuracy is also presented.
| Year | Citations | |
|---|---|---|
Page 1
Page 1