Schottky Barrier Carbon Nanotube Transistor: Compact Modeling, Scaling Study, and Circuit Design Applications

TLDR

The study develops a physics‑based compact model for Schottky‑barrier CNTFETs, performs a scaling analysis of device parameters, designs logic circuits to evaluate SB effects, and proposes a three‑valued static memory for high‑density integration. The model analytically captures channel charge influenced by source and drain SBs, is validated against simulation, Monte Carlo, and experimental data, and is applied in scaling studies, logic circuit design, and a three‑valued memory prototype. The model shows good agreement with experimental data across a wide range of gate and drain biases.

Abstract

This paper presents a computationally efficient physics-based compact model for the Schottky barrier (SB) carbon nanotube field-effect transistor (CNTFET). This compact model includes a new analytical formulation of the channel charge, taking into account the influence of the source and drain SBs. Compact model simulation results (- characteristic and channel density of charge) as well as Monte Carlo simulation results, which are provided by a recent work, will be given and compared to each other and also to experimental data to validate the used approximations. Good agreement is observed over a large range of gate and drain biases. Furthermore, a scaling study is presented to examine the impact of technological parameters on the device figure of merit. Then, for the assessment of the SB on circuit performances, traditional logical circuits are designed using the SB-CNTFET compact model, and results are compared with a conventional CNTFET with zero-SB height. Finally, exploiting the particular properties of SB-CNTFETs, a three-valued static memory that is suitable for high density integration is presented.