SOI TFET $I_{\rm ON}/I_{\rm OFF}$ Enhancement via Back Biasing

Abstract

The effect of back biasing on the performance of a planar tunnel field-effect transistor (TFET) implemented on a silicon-on-insulator substrate is investigated. It is found that reverse back biasing reduces the subthreshold swing SS and increases the range of drain current over which SS is less than ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">q</i> ) <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ln</i> (10); hence, it is effective for improving the TFET on/off current ratio for low operating voltages (≤ 0.5 V).