JPEG encoder for low-cost FPGAs

Abstract

This paper presents the implementation of a JPEG encoder that exploits minimal usage of FPGA resources. The encoder compresses an image as a stream of 8×8 blocks with each element of the block applied and processed individually. The zigzag unit typically found in implementations of JPEG encoders is eliminated. The division operation of the quantization step is replaced by a combination of multiplication and shift operations. The encoder is implemented on Xilinx Spartan-3 FPGA and is benchmarked against two software implementations on four test images. It is demonstrated that it yields performance of similar quality while requiring very limited FPGA resources. A co-emulation technique is applied to reduce development time and to test and verify the encoder design.