Publication | Open Access
Vertical Surrounding Gate Transistors Using Single InAs Nanowires Grown on Si Substrates
95
Citations
21
References
2010
Year
Semiconductor TechnologyElectrical EngineeringElectronic DevicesEngineeringSemiconductor DeviceNanotechnologySi SubstratesApplied PhysicsNanowire DiameterThreshold VoltageSemiconductor Device FabricationSilicon On InsulatorSingle Inas NanowiresSemiconductor Nanostructures
We report on the fabrication and characterization of vertical InAs nanowire channel field effect transistors (FETs) with high-k/metal gate-all-around structures. Single InAs nanowires were grown on Si substrates by the selective-area metalorganic vapor phase epitaxy method. The resultant devices exhibited n-channel FET characteristics with a threshold voltage of around -0.1 V. The best device exhibited maximum drain current (IDSmax/wG), maximum transconductance (gmmax/wG), on–off ratio (ION/OFF), subthreshold slope (SS) of 83 µA/µm, 83 µS/µm, 104, and 320 mV/decade, respectively, for a nanowire diameter of 100 nm.
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