Soft Information for LDPC Decoding in Flash: Mutual-Information Optimized Quantization

TLDR

High‑capacity NAND flash uses multi‑level cells to store multiple bits per cell, but the resulting higher raw bit‑error rates demand powerful error‑correction coding. The study investigates applying low‑density parity‑check (LDPC) codes to NAND flash in order to approach channel capacity. Soft information for the LDPC decoder is obtained by performing multiple reads at optimized word‑line voltages chosen to maximize mutual information between the channel input and output. The approach yields significant performance gains, allowing LDPC decoding to outperform BCH codes across a range of block error rates.

Abstract

High-capacity NAND flash memory can achieve high density storage by using multi-level cells (MLC) to store more than one bit per cell. Although this larger storage capacity is certainly beneficial, the increased density also increases the raw bit error rate (BER), making powerful error correction coding necessary. Traditional flash memories employ simple algebraic codes, such as BCH codes, that can correct a fixed, specified number of errors. This paper investigates the application of low-density parity-check (LDPC) codes which are well known for their ability to approach capacity in the AWGN channel. We obtain soft information for the LDPC decoder by performing multiple cell reads with distinct word-line voltages. The values of the word-line voltages (also called reference voltages) are optimized by maximizing the mutual information between the input and output of the multiple-read channel. Our results show that using this soft information in the LDPC decoder provides a significant benefit and enables us to outperform BCH codes over a range of block error rates.