FPGA implementation of a coherent SOQPSK-TG demodulator

Abstract

In this paper, we present a hardware implementation of a demodulator for shaped offset quadrature phase shift keying, telemetry group version (SOQPSK-TG). The demodulator is implemented based on maximum likelihood sequence detection of SOQPSK using the soft-output Viterbi algorithm (SOVA). Symbol timing and carrier phase recovery are fundamental operations required for the best symbol detection. We describe how to generate time and phase error signals from the SOVA which are fed in two separate discrete phase locked loops (PLLs). The PLLs work along with other blocks including a down converter, matched filters and the SOVA in order to provide optimal sequence detection of the received signal from analog to digital converter. Additionally, the SOVA provides output reliabilities for the detected bits which can be used by iterative error correction schemes such as low-density parity-check (LDPC) codes. Moreover, we propose a simplified implementation of the SOVA based on the two-traceback method which reduces the overall size of the demodulator by 25%. The simplification causes a slight degradation in the output reliabilities which is examined by LDPC decoding of its output. The demodulator is targeted for field programmable gate arrays (FPGAs) which provide us with flexibility and rapid prototyping. Finally, the FPGA performance and utilization results along with bit error rate performance of both demodulator and LDPC coded system are presented.