Relationship between trapped holes and interface states in MOS capacitors

Abstract

Metal–silicon-dioxide–silicon capacitors with dry-grown oxides, when stressed at fields of 7.1–7.5 MV/cm with field plate positive at 90 K, showed buildup of trapped holes. Interface states appeared only after the samples were warmed. The number of interface states generated in one hour at either 20 or 66 °C was linearly proportional to the number of trapped holes, and the number of states generated in the central 0.7-eV portion of the Si bandgap during one year’s storage at room temperature was essentially equal to the original number of trapped holes. These results provide quantitative evidence of a cause and effect relationship between trapped holes and interface states in the Si-SiO2 system.