A 0.08 mm<sup>2</sup>, 7mW Time-Encoding Oversampling Converter with 10 bits and 20MHz BW in 65nm CMOS

Abstract

This work presents an area- and power-efficient realization of a new Time-Encoding Oversampling Converter (TEOC) consisting of a 3rd-order CT loop filter and a self-oscillating PWM which displays similar performance than a standard multibit CT-ΣΔ modulator but has the complexity of a single bit design. The introduced Time-Encoding Quantizer (TEQ) is implemented inside a ΣΔ modulator by replacing a multibit quantizer. An innovative TEQ is used to overcome design issues in a 1.0V supply-voltage 65nm digital CMOS technology. The TEQ allows an exchange of amplitude-resolution by time-resolution. The approach of time-resolution alleviates the scaling difficulties of mixed-signal circuits in nano-scale technologies. The TEOC features a 63dB dynamic-range and a peak-SNDR of 61 dB over a 20MHz signal bandwidth. Clocked at 2.5GHz, the complete ADC consumes 7mW from a single 1.0V supply, including also the reference buffers. The ADC core results in an attractively small area of 0.08mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and in a Figure-of-Merit (FoM=Pwr/2 BW 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ENOB</sup> ) of 0.17pJ/conversion-step.