Electrothermal engineering in the nanometer era

Abstract

Management of electrothermal (ET) issues arising due to power dissipation both at the micro- and macro- scale is central to the development of future generation microprocessors, integrated networks, and other highly integrated circuits and systems. This paper will provide a broad overview of various ET effects in nanoscale VLSI and highlight both technology and design choices that are thermally-aware. First, effects at the micro scale---in interconnects and devices and their implications for performance, reliability and design are discussed. Next, macro scale---circuit and system level issues including substrate temperature gradients as well as strong ET couplings between supply voltage, frequency, power dissipation and junction temperature in leakage dominant technologies are outlined. A recently developed system level ET analysis methodology and tool that comprehends ET couplings in a self-consistent manner and can generate accurate thermal profile of the substrate is summarized. The application of the ET-tool is demonstrated in a number of areas from power-performance-cooling cost tradeoff analysis to circuit optimization, full-chip leakage estimation, and temperature/reliability aware design space generation. Implications of chip cooling for nanometer scale bulk and SOI based CMOS technologies are also discussed. The ET analysis tool is also shown to be useful for hot-spot management. The paper ends with a brief discussion of electrothermal issues in emerging 3-D ICs and highlights the advantages of employing hybrid Carbon Nanotube-Cu interconnects in both 2-D and 3-D designs.