A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits

Abstract

A technique of constructing dual-rail muller pipelines tolerant to transient faults is proposed. The pipeline datapath is either an NCL-D or NCL-X circuit. A dedicated controller implements the error recovery protocol, which significantly improves fault tolerance with respect to the earlier rail synchronization method. A case study featuring transient fault simulation is presented.