NMOS-inside 6T SRAM layout reducing neutron-induced multiple cell upsets

Abstract

This paper presents a novel NMOS-inside 6T SRAM cell layout that reduces a neutron-induced MCU SER on a same wordline. We implemented a 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-inside 6T SRAM cells.