Modeling and optimization of the chip level program disturbance of 3D NAND Flash memory

Abstract

The effects of three types of program (PGM) disturbance, which are X, XY, and Y mode, on the chip level erase (ERS) threshold voltage (VT) distribution in three-dimensional (3D) NAND Flash memory were studied. A simple model was constructed to emulate both the chip operation and PGM characteristics. It was found that the right tail and peak of ERS VT distribution after PGM operation of a physical block are determined by Y mode and other two modes respectively. We concluded that the difference in channel (CH) boosting level between Y mode and other two modes should be achieved less than a width of initial ERS VT distribution in order not to degrade its right tail. The optimal PGM operation conditions for high CH boosting level were proposed to minimize the band-to-band tunneling (BTBT) current in the dummy WL region.